Metal-insulator-metal (mim) capacitor structure and method for forming the same

ABSTRACT

A metal-insulator-metal (MIM) capacitor structure and method for forming MIM capacitor structure are provided. The MIM capacitor structure includes a substrate and a metal-insulator-metal (MIM) capacitor formed on the substrate. The MIM capacitor includes a capacitor top metal (CTM) layer, a capacitor bottom metal (CBM) layer and an insulator formed between the CTM layer and the CBM layer. The insulator includes an insulating layer and a first high-k dielectric layer, and the insulating layer includes a nitride layer and an oxide layer, and the nitride layer is formed between the first high-k dielectric layer and the oxide layer.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a Continuation-In-Part of application Ser. No.14/133,037, filed on Dec. 18, 2013 and entitled “MECHANISMS FOR FORMINGMETAL-INSULATOR-METAL (MIM) CAPACITOR STRUCTURE”.

BACKGROUND

Semiconductor devices are used in a variety of electronic applications,such as personal computers, cell phones, digital cameras, and otherelectronic equipment. Semiconductor devices are typically fabricated bysequentially depositing insulating or dielectric layers, conductivelayers, and semiconductive layers of material over a semiconductorsubstrate, and patterning the various material layers using lithographyto form circuit components and elements thereon. Many integratedcircuits are typically manufactured on a single semiconductor wafer, andindividual dies on the wafer are singulated by sawing between theintegrated circuits along a scribe line. The individual dies aretypically packaged separately, in multi-chip modules, or in other typesof packaging, for example.

The semiconductor industry continues to improve the integration densityof various electronic components (e.g., transistors, diodes, resistors,capacitors, etc.) by continual reductions in minimum feature size, whichallow more components to be integrated into a given area. These smallerelectronic components also require smaller packages that utilize lessarea than packages of the past, in some applications.

One type of capacitor is a metal-insulator-metal (MIM) capacitor, whichis used in mixed signal devices and logic devices, such as embeddedmemories and radio frequency devices. MIM capacitors are used to store acharge in a variety of semiconductor devices. A MIM capacitor is formedhorizontally on a semiconductor wafer, with two metal plates sandwichinga dielectric layer parallel to the wafer surface. However, there aremany challenges related to the MIM capacitor.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIG. 1 shows a cross-sectional representation of a semiconductor devicestructure, in accordance with some embodiments of the disclosure.

FIG. 2 shows a cross-sectional representation of a metal-insulator-metal(MIM) capacitor structure, in accordance with some embodiments of thedisclosure.

FIGS. 3A-3C show cross-sectional representations of various stages offorming a metal-insulator-metal (MIM) capacitor structure, in accordancewith some embodiments of the disclosure.

FIGS. 4A-4E show cross-sectional representations of forming ametal-insulator-metal (MIM) capacitor structure, in accordance with someembodiments of the disclosure.

FIG. 5 shows a cross-sectional representation of a metal-insulator-metal(MIM) capacitor structure, in accordance with some embodiments of thedisclosure.

FIGS. 6A-6E show cross-sectional representations of forming ametal-insulator-metal (MIM) capacitor structure, in accordance with someembodiments of the disclosure.

FIGS. 7A-7B show cross-sectional representations of forming ametal-insulator-metal (MIM) capacitor structure, in accordance with someembodiments of the disclosure.

FIG. 8 shows a cross-sectional representation of a metal-insulator-metal(MIM) capacitor structure, in accordance with some embodiments of thedisclosure.

FIG. 9 shows a cross-sectional representation of a metal-insulator-metal(MIM) capacitor structure, in accordance with some embodiments of thedisclosure.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Some variations of the embodiments are described. Throughout the variousviews and illustrative embodiments, like reference numbers are used todesignate like elements. It is understood that additional operations canbe provided before, during, and after the method, and some of theoperations described can be replaced or eliminated for other embodimentsof the method.

Embodiments of mechanisms for forming a metal-insulator-metal (MIM)capacitor structure are provided. FIG. 1 shows a cross-sectionalrepresentation of a semiconductor device structure 100, in accordancewith some embodiments of the disclosure. Semiconductor device structure100 includes a metal-insulator-metal (MIM) capacitor structure 150 a.

As shown in FIG. 1, a substrate 102 is provided. Substrate 102 includesa MIM region 11 and a non-MIM region 12. Substrate 102 may be made ofsilicon or other semiconductor materials. Alternatively or additionally,substrate 102 may include other elementary semiconductor materials suchas germanium. In some embodiments, substrate 102 is made of a compoundsemiconductor such as silicon carbide, gallium arsenic, indium arsenide,or indium phosphide. In some embodiments, substrate 102 is made of analloy semiconductor such as silicon germanium, silicon germaniumcarbide, gallium arsenic phosphide, or gallium indium phosphide. In someembodiments, substrate 102 includes an epitaxial layer. For example,substrate 102 has an epitaxial layer overlying a bulk semiconductor.

Substrate 102 may further include isolation features 104, such asshallow trench isolation (STI) features or local oxidation of silicon(LOCOS) features. The isolation features may define and isolate variousintegrated circuit devices. Integrated circuit devices, such as metaloxide semiconductor field effect transistors (MOSFET), complementarymetal oxide semiconductor (CMOS) transistors, bipolar junctiontransistors (BJT), high-voltage transistors, high-frequency transistors,p-channel and/or n-channel field effect transistors (PFETs/NFETs),etc.), diodes, or other suitable elements, are formed in and/or onsubstrate 102.

As shown in FIG. 1, a gate stack 106 is formed on substrate 102. Gatestack 106 includes a gate dielectric layer 108, a gate electrode layer110 formed on gate dielectric layer 108. Gate dielectric layer 108 ismade of silicon oxide, silicon nitride, or a high dielectric constantmaterial (high-k material). Gate electrode layer 110 is made ofpolysilicon or metal material. Gate spacers 112 are formed on sidewallsof gate stack 106. In some embodiments, gate spacers 112 are made ofsilicon oxide, silicon nitride, and/or silicon oxynitride.

Source/drain regions 114 are formed in substrate 102. An inter-layerdielectric (ILD) layer 116 is formed on substrate 102, and a contactstructure 118 is formed in ILD layer 116. Contact structures 118 areformed in ILD layer 116 and in contact with source/drain regions 114.Contact structures 118 are made of conductive materials, such as copper,or copper alloy.

As shown in FIG. 1, an interconnect structure 120 is formed oversubstrate 102. In some embodiments, interconnect structure 120 includingmetal lines 124 and vias 126 is embedded in inter-metal dielectric (IMD)layers 122. In some embodiments, interconnect structure 120 is formed ina back-end-of-line (BEOL) process. Metal lines 124 and vias 126 may bemade of a conductive material, such as copper (Cu), aluminum (Al),tungsten (W), or other applicable materials. In some embodiments, metallines 124 and vias 126 are copper or copper alloy. In some embodiments,metal lines 124 and vias 126 are formed by single and/or dual damasceneprocesses. Metal lines 124 include multiple metal layers (namely M1, M2,M3 . . . , and Mtop) which are interconnected through vias 126.

In some embodiments, inter-metal dielectric (IMD) layers 122 are made ofsilicon oxide. In some other embodiments, IMD layers 122 are made ofun-doped silicate glass (USG), fluorinated silicate glass (FSG),carbon-doped silicate glass, silicon nitride or silicon oxynitride. Insome embodiments, IMD layers 122 include multiple dielectric layers. Oneor more of the multiple dielectric layers are made of low dielectricconstant (low-k) materials, such as a dielectric constant of less thanabout 3.0, or less than about 2.5. Interconnect structure 120 shown inFIG. 1 is merely for illustrative purposes. Interconnect structure 120may include other configurations and may include one or more metal linesand IMD layers.

As shown in FIG. 1, an MIM capacitor structure 150 a is formed oversubstrate 102 in MIM region 11. MIM capacitor structure 150 a is asandwich structure and an insulating layer 154 is formed between acapacitor bottom metal (CBM) layer 152 and a capacitor top metal (CTM)layer 158.

As shown in FIG. 1, in MIM region 11, one of vias 116 is formed in IMDlayer 122 to electrically connect CBM layer 152, and one of vias 116 isformed in IMD layer 122 to electrically connect CTM layer 158. In thenon-MIM region, one of vias 116 is formed in IMD layer 122 toelectrically connect metal line 124. A top metal layer 160 (also calledM_(top)) is formed over vias 116 and in a top IMD layer 162. Top metallayer 160 is furthest away from the first metal layer M₁.

FIG. 2 shows a cross-sectional representation of metal-insulator-metal(MIM) capacitor structure 150 a, in accordance with some embodiments ofthe disclosure.

As shown in FIG. 2, CBM layer 152 includes a bottom barrier layer 152 a,a main metal layer 152 b and a top barrier layer 152 c. Bottom barrierlayer 152 a and top barrier layer 152 c are used as anti-oxidation layerto protect main metal layer 152 b from being oxidized. In addition, topbarrier layer 152 c is used as an adhesion layer to improve the adhesionbetween main metal layer 152 b and insulating layer 154. Bottom barrierlayer 152 a and top barrier layer 152 c independently include titanium(Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN).In some embodiments, main metal layer 152 b is made of copper (Cu),copper alloy, aluminum (Al), aluminum (Al) alloy, copper aluminum alloy(AlCu), tungsten (W) or tungsten (W) alloy.

CBM layer 152 is formed by a procedure including depositing,photolithography, and etching processes. The deposition processesinclude chemical vapor deposition (CVD), physical vapor deposition(PVD), atomic layer deposition (ALD), or applicable methods. Thephotolithography processes include photoresist coating (e.g., spin-oncoating), soft baking, mask aligning, exposure, post-exposure baking,developing the photoresist, rinsing, and drying (e.g., hard baking). Theetching processes include dry etching, wet etching, and/or other etchingmethods.

Insulating layer 154 is made of dielectric materials, such as siliconoxide, silicon nitride or silicon glass. In some embodiments, insulatinglayer 154 is formed by a chemical vapor deposition (CVD) or physicalvapor deposition (PVD). In some embodiments, insulating layer 154 has athickness T₁ in a range from about 7 angstrom to about 10000 angstrom.

In addition, CTM layer 158 includes a bottom barrier layer 158 a, a mainmetal layer 158 b and a top barrier layer 158 c. The material andfabrication method of bottom barrier layer 158 a, a main metal layer 158b and a top barrier layer 158 c are like these of bottom barrier layer152 a, main metal layer 152 b and top barrier layer 152 c, respectively.

The capacitance of capacitor structure 150 a is calculated by followingEquation (I). From the Equation (I), the capacitance of MIM capacitorstructure 150 a is proportional to K value and inversely proportional tod value.

C (capacitance)=K∈ ₀ A/d  Equation (I)

-   -   ∈₀: the permittivity of free space;    -   K: the relative dielectric constant of insulating layer 154;    -   A: the area of overlap of the two plates (CBM layer 152 and CTM        layer 158);    -   d: the thickness T₁ of insulating layer 154.

In addition, the maximum energy that can be stored safely in MIMcapacitor structure 150 a is limited by the breakdown voltage.Especially for a high-voltage device, breakdown voltage is a main factoraffecting the performance of MIM capacitor structure 150 a. In addition,the breakdown voltage is proportional to the thickness T₁ of insulatinglayer 154.

In some embodiments, in order to increase the breakdown voltage of MIMcapacitor structure 150 a, the thickness T₁ of the insulating layer isincreased. However, if the K value and A value are constant, thecapacitance of MIM capacitor structure 150 a is decreased when thicknessT₁ of insulating layer 154 is increased according to Equation (I). Inorder to maintain the same capacitance value of MIM capacitor structure150 a, the K value is increased along with increase in thickness T₁ ofinsulating layer 154. Therefore, in some embodiments, insulating layer154 with a high-k dielectric layer is provided.

FIGS. 3A-3C show cross-sectional representations of various stages offorming a metal-insulator-metal (MIM) capacitor structure 150 b, inaccordance with some embodiments of the disclosure.

As shown in FIG. 3A, in MIM region 11, CBM layer 152 includes bottombarrier layer 152 a, main metal layer 152 b and top barrier layer 152 c.

After CBM layer 152 is formed, a high-k dielectric layer 153 is formedon top barrier layer 152 c as shown in FIG. 3B in accordance with someembodiments of the disclosure. In some embodiments, high-k dielectriclayer 153 is made of titanium oxide (Ti_(x)O_(y), x is a real number andy is a real number), tantalum oxide (Ta_(x)O_(y), x is a real number andy is a real number), titanium oxide nitride (Ti_(x)O_(y)N_(z), x is areal number, y is a real number and z is a real number) or tantalumoxide Nitride (Ta_(x)O_(y)N_(z), x is a real number, y is a real numberand z is a real number). In some embodiments, high-k dielectric layer153 has a relative dielectric constant (the K value) in a range from 4to about 400. In some embodiments, high-k dielectric layer 153 has athickness T₂ in a range from about 5 angstrom to about 50 angstrom.

High-k dielectric layer 153 is formed by treating a surface of topbarrier layer 152 c of CBM layer 152. The treating is performed byimplanting or supplying oxygen ions to a surface of top barrier layer152 c of CBM layer 152. In some embodiments, the treating methodincludes a plasma ionization method, microwave surface downstreamionization method, or furnace/rapid thermal annealing (RTA) method.

In some embodiments, when the plasma ionization method is used, plasmawith nitrous oxide (N₂O), water (H₂O), nitric oxide (NO) or oxygen (O₂)is used to oxidize top barrier layer 152 c to form high-k dielectriclayer 153. In some embodiments, the plasma ionization method isperformed at a pressure in a range from about 0.1 μtorr to about 1000torr.

In some embodiments, when the microwave surface downstream ionizationmethod is used, a process gas including nitrous oxide (N₂O), water(H₂O), nitric oxide (NO) or oxygen (O₂) is used. In some embodiments,the power of the microwave is in a range from about 10 W to about 10000W. In some embodiments, the frequency of the microwave is in a rangefrom about 1 MHz to about 100 GHz.

In some embodiments, when the furnace/rapid thermal annealing (RTA)method is used, a process gas including nitrous oxide (N₂O), water(H₂O), nitric oxide (NO), oxygen (O₂) or ozone (O₃) is used. In someembodiments, the temperature used in the furnace/rapid thermal annealing(RTA) method is in a range from about 100° C. to about 1200° C. In someembodiments, the operation time used in furnace/rapid thermal annealing(RTA) method is in a range from about 1 s to about 1000 s.

After high-k dielectric layer 153 is formed, insulating layer 154 isformed on high-k dielectric layer 153 as shown in FIG. 3C in accordancewith some embodiments of the disclosure. An insulator 15 of MIMcapacitor structure 150 b is constructed by insulating layer 154 andhigh-k dielectric layer 153.

It should be noted that, when the capacitance of MIM capacitor structure150 b is the same as that of MIM capacitor structure 150 a, the relativedielectric constant (the K value) of insulator 15 is increased by addinghigh-k dielectric layer 153, and therefore the thickness of insulator 15is increased. In some embodiments, a sum of the thickness T₁′ ofinsulating layer 154 and the thickness T₂ of high-k dielectric layer 153is in a range from about 12 angstrom to about 10050 angstrom.

When the thickness of insulator 15 (or insulating layer 154) isincreased, the process window for forming insulator 15 (or insulatinglayer 154) is improved. In addition, once the thickness of insulator 15is increased, the breakdown voltage of MIM capacitor structure 150 b isimproved without reducing capacitance.

FIGS. 4A-4E shows a cross-sectional representation of forming ametal-insulator-metal (MIM) capacitor structure, in accordance with someembodiments of the disclosure.

As shown in FIG. 4A, CBM layer 152 includes bottom barrier layer 152 a,main metal layer 152 b and top barrier layer 152 c.

After CBM layer 152 is formed, high-k dielectric layer 153 is formed ontop barrier layer 152 c as shown in FIG. 4B in accordance with someembodiments of the disclosure. The fabricating method of high-kdielectric layer 153 in FIG. 4B is the same as that in FIG. 3B.

After high-k dielectric layer 153 is formed, insulating layer 154 isformed on high-k dielectric layer 153 as shown in FIG. 4C in accordancewith some embodiments of the disclosure. Afterwards, a barrier layer 155is formed on insulating layer 154. In some embodiments, barrier layer155 is made of titanium (Ti), titanium nitride (TiN), tantalum (Ta), ortantalum nitride (TaN).

In some embodiments, barrier layer 155 has a thickness T₃ is in a rangefrom about 5 angstrom to about 50 angstrom. If the thickness T₃ ofbarrier layer 155 is too thick, barrier layer 155 may be oxidizedinsufficiently later. Therefore, an un-oxidated barrier layer may beformed between high-k dielectric layer 157 (formed afterwards, shown inFIG. 4D) and insulating layer 154. If the thickness T₃ of barrier layer155 is too thin, it is hard to enhance the breakdown voltage.

After barrier layer 155 is formed, a second high-k dielectric layer 157is formed on insulating layer 154 as shown in FIG. 4D in accordance withsome embodiments of the disclosure. In some embodiments, second high-kdielectric layer 157 has a relative dielectric constant (the K value) ina range from about 4 to about 400. In some embodiments, second high-kdielectric layer 157 has a thickness T₄ in a range from about 5 angstromto about 50 angstrom.

Second high-k dielectric layer 157 is formed by treating a surface ofbarrier layer 155. The treatment is performed by implanting or supplyingoxygen ions to a surface of barrier layer 155. In some embodiments, thetreatment method includes a plasma ionization method, microwave surfacedownstream ionization method, or furnace/rapid thermal annealing (RTA)method.

In some embodiments, when the plasma ionization method is used, plasmawith nitrous oxide (N₂O), water (H₂O), or nitric oxide (NO), oxygen (O2)or ozone (O₃) is used to oxidize barrier layer 155. In some embodiments,the plasma ionization method is performed at a pressure in a range fromabout 0.1 μtorr to about 1000 torr.

In some embodiments, when the microwave surface downstream ionizationmethod is used, a process gas including nitrous oxide (N₂O), water(H₂O), or nitric oxide (NO), oxygen (O₂) or ozone (O₃) is used. In someembodiments, the power of the microwave is in a range from about 10 W toabout 10000 W. In some embodiments, the frequency of the microwave is ina range from 1 MHZ to about 1000 MHZ.

In some embodiments, when the furnace/rapid thermal annealing (RTA)method is used, a process gas includes nitrous oxide (N₂O), water (H₂O),or nitric oxide (NO), oxygen (O₂) or ozone (O₃) is used. In someembodiments, the temperature used in furnace/rapid thermal annealing(RTA) method is in a range from about 100° C. to about 1200° C. In someembodiments, the operation time used in the furnace/rapid thermalannealing (RTA) method is in a range from about 1 s to about 1000 s.

As shown in FIG. 4D, insulator 15 is constructed by first high-kdielectric layer 153, insulating layer 154 and second high-k dielectriclayer 157. In some embodiments, a sum of the thickness T₁″ of insulatinglayer 154, the thickness T₂ of high-k dielectric layer 153 and thethickness T₄ of second high-k dielectric layer 157 is in a range fromabout 17 angstrom to about 10100 angstrom.

After second high-k dielectric layer 157 is formed, CTM layer 158 isformed on second high-k dielectric layer 157 as shown in FIG. 4E inaccordance with some embodiments of the disclosure. CTM layer 158includes a bottom barrier layer 158 a, main metal layer 158 b and topbarrier layer 158 c. After CTM layer 158 is formed, a MIM capacitorstructure 150 c is obtained.

It should be noted that the relative dielectric constant (the K value)of insulator 15 is increased by adding high-k dielectric layer 153 andsecond high-k dielectric layer 157, and therefore the thickness ofinsulator 15 is increased.

When the sum of the thickness of insulator 15 (or insulating layer 154)is increased, the process window for forming insulator 15 (or insulatinglayer 154) is improved. In addition, once the sum of the thickness ofinsulator 15 is increased, the breakdown voltage of MIM capacitorstructure 150 c is further improved without reducing capacitance.

FIG. 5 shows a cross-sectional representation of a metal-insulator-metal(MIM) capacitor structure 150 d, in accordance with some embodiments ofthe disclosure. FIG. 5 is similar to FIG. 4E, with the differencebetween FIG. 5 and FIG. 4E being that no high-k dielectric layer 153 isformed in FIG. 5.

As shown in FIG. 5, MIM capacitor structure 150 d is formed with secondhigh-k dielectric layer 157. Insulator 15 is constructed by insulatinglayer 154 and second high-k dielectric layer 157. In some embodiments,the sum of the thickness T₁′″ of insulating layer 154 and the thicknessT₄ of second high-k dielectric layer 157 is in a range from about 12angstrom to about 10050 angstrom.

The advantage for forming second high-k dielectric layer 157 is toincrease the relative dielectric constant (the K value) of MIM capacitorstructure 150 d. Therefore, the thickness of insulator 15 is increasedalong with the increased K value, and breakdown voltage is improved.Furthermore, the process window for forming insulator 15 (or insulatinglayer 154) is improved.

FIG. 6A-6E show cross-sectional representations of ametal-insulator-metal (MIM) capacitor structure 150 e, in accordancewith some embodiments of the disclosure.

Referring to FIG. 6A, in MIM region 11, CBM layer 152 includes bottombarrier layer 152 a, main metal layer 152 b and top barrier layer 152 c.

After CBM layer 152 is formed, a high-k dielectric layer 153 is formedon top barrier layer 152 c as shown in FIG. 6B in accordance with someembodiments of the disclosure. In some embodiments, high-k dielectriclayer 153 is made of titanium oxide (Ti_(x)O_(y), x is a real number andy is a real number), tantalum oxide (Ta_(x)O_(y), x is a real number andy is a real number), titanium oxide nitride (Ti_(x)O_(y)N_(z), x is areal number, y is a real number and z is a real number) or tantalumoxide Nitride (Ta_(x)O_(y)N_(z), x is a real number, y is a real numberand z is a real number). In some embodiments, high-k dielectric layer153 has a relative dielectric constant (the K value) in a range from 4to about 400.

High-k dielectric layer 153 is formed by treating a surface of topbarrier layer 152 c of CBM layer 152. The treatment is performed byimplanting or supplying oxygen ions to a surface of top barrier layer152 c of CBM layer 152. In some embodiments, the treatment methodincludes a plasma ionization method, a microwave surface downstreamionization method, or a furnace/rapid thermal annealing (RTA) method.

In some embodiments, when the plasma ionization method is used, plasmawith nitrous oxide (N₂O), water (H₂O), nitric oxide (NO) or oxygen (O₂)is used to oxidize top barrier layer 152 c to form high-k dielectriclayer 153. In some embodiments, the plasma ionization method isperformed at a pressure in a range from about 0.1 μtorr to about 1000torr.

In some embodiments, when the microwave surface downstream ionizationmethod is used, a process gas including nitrous oxide (N₂O), water(H₂O), nitric oxide (NO) or oxygen (O₂) is used. In some embodiments,the power of the microwave is in a range from about 10 W to about 10000W. In some embodiments, the frequency of the microwave is in a rangefrom about 1 MHz to about 100 GHz.

In some embodiments, when the furnace/rapid thermal annealing (RTA)method is used, a process gas including nitrous oxide (N₂O), water(H₂O), nitric oxide (NO), oxygen (O₂) or ozone (O₃) is used. In someembodiments, the temperature used in the furnace/rapid thermal annealing(RTA) method is in a range from about 100° C. to about 1200° C. In someembodiments, the operation time used in furnace/rapid thermal annealing(RTA) method is in a range from about 1 s to about 1000 s.

After high-k dielectric layer 153 is formed, a nitride layer 154 a isformed on high-k dielectric layer 153 as shown in FIG. 6C in accordancewith some embodiments of the disclosure. In some embodiments, nitridelayer 154 a is silicon nitride. In some embodiments, nitride layer 154 ais formed by a deposition process. The deposition process includeschemical vapor deposition (CVD), physical vapor deposition (PVD), atomiclayer deposition (ALD), or other applicable processes.

After nitride layer 154 a is formed, an oxide layer 154 b is formed onnitride layer 154 a as shown in FIG. 6D in accordance with someembodiments of the disclosure. Insulating layer 154 is constructed bynitride layer 154 a and oxide layer 154 b. In some embodiments, nitridelayer 154 a is silicon nitride, and oxide layer 154 b is silicon oxide.

It should be noted that some pin-holes are unavoidably formed in nitridelayer 154 a, and electrons may transport from one layer to another layervia the pin-holes. Therefore, a leakage problem may occur and breakdownvoltage may be decreased further. In order to solve the leakage problem,oxide layer 154 b is formed by treating a top surface of nitride 154 a.The treating is performed by implanting or supplying oxygen ions to thetop surface of nitride layer 154 a.

In some embodiments, the treating method includes a plasma ionizationmethod, a microwave surface downstream ionization method, or afurnace/rapid thermal annealing (RTA) method.

In some embodiments, when the plasma ionization method is used, plasmawith nitrous oxide (N₂O), water (H₂O), nitric oxide (NO) or oxygen (O₂)is used to oxidize nitride layer 154 a to form oxide layer 154 b. Insome embodiments, the plasma ionization method is performed at apressure in a range from about 0.1 μtorr to about 1000 torr. In someembodiments, the plasma ionization method is performed at RF power in arange from about 10 W to about 10000 W. In some embodiments, the plasmaionization method is performed for a period of time in a range fromabout 1 second seconds to about 1000 seconds.

After oxide layer 154 b is formed, CTM layer 158 is formed on oxidelayer 154 b as shown in FIG. 6E in accordance with some embodiments ofthe disclosure. CTM layer 158 includes a bottom barrier layer 158 a, amain metal layer 158 b and a top barrier layer 158 c.

It should be noted that the pin-holes in each of the layers are atdifferent locations, and therefore the electrons are not more likely topass through the multiple layers than the single layer. Therefore, thepath for transporting electrons through two layers of insulating layer154 is longer. When the path is increased, the leakage problem may beresolved and further breakdown voltage of MIM structure is increased.

FIGS. 7A-7B shows a cross-sectional representation of forming ametal-insulator-metal (MIM) capacitor structure 150 f, in accordancewith some embodiments of the disclosure.

Referring to FIG. 7A, nitride layer 154 a is formed on CBM layer 152,oxide layer 154 b is formed on nitride layer 154 a, and a second nitridelayer 154 c is formed on oxide layer 154 b. In some embodiments, secondnitride layer 154 c is deposited on oxide layer 154 b.

After second nitride layer 154 c is formed, a second oxide layer 154 dis formed on second nitride layer 154 c as shown in FIG. 7B inaccordance with some embodiments of the disclosure. Afterwards, CTMlayer 158 is formed on second nitride layer 154 c. Insulating layer 154is constructed by nitride layer 154 a, oxide layer 154 b, second nitridelayer 154 c and second oxide layer 154 d.

It should be noted that insulating layer 154 is made of four layers. Thetransporting path of the electrons in the multiple layers is longer thanin the single layer, and therefore the occurrence of leakage current isdecreased and further breakdown voltage of the MIM structure isincreased.

FIG. 8 shows a cross-sectional representation of a metal-insulator-metal(MIM) capacitor structure 150 g, in accordance with some embodiments ofthe disclosure. As shown in FIG. 8, insulating layer 154 is betweenhigh-k dielectric layer 153 and high-k dielectric layer 157. Insulatinglayer 154 is made of two layers including nitride layer 154 a and oxidelayer 154 b. Compared with FIG. 4E, insulating layer 154 in FIG. 8 isformed by two layers, and it has a lower refractive index.

FIG. 9 shows a cross-sectional representation of a metal-insulator-metal(MIM) capacitor structure 150 h, in accordance with some embodiments ofthe disclosure.

Insulating layer 154 is between high-k dielectric layer 153 and high-kdielectric layer 157. Insulating layer 154 is made of four layersincluding nitride layer 154 a, oxide layer 154 b, second nitride layer154 c and second oxide layer 154 d.

Embodiments of mechanisms for forming a metal-insulator-metal (MIM)capacitor structure are provided. The MIM capacitor structure is made ofa CBM layer, a main metal layer and a CTM layer. The insulating layerincludes a high-k dielectric layer, and/or a second high-k dielectriclayer. A first high-k dielectric layer is formed on the CBM layer andthe insulating layer. A second high-k dielectric layer is formed on theinsulating layer and the CTM layer. The high-k dielectric layer is usedto improve the K value of MIM capacitor structure. Once the K value isincreased, the thickness of the insulating layer is also increasedwithout reducing the capacitance. Therefore, breakdown voltage isimproved and the process window for forming the insulating layer isimproved. In addition, the insulating layer is formed by a single layeror a multiple layers. Compared to a MIM structure with a single-layeredinsulating layer, a MIM structure with a multi-layered insulating layerhas a higher break down voltage.

In some embodiments, a metal-insulator-metal (MIM) capacitor structureis provided. The MIM capacitor structure includes a substrate and ametal-insulator-metal (MIM) capacitor formed on the substrate. The MIMcapacitor includes a capacitor top metal (CTM) layer, a capacitor bottommetal (CBM) layer and an insulator formed between the CTM layer and theCBM layer. The insulator includes an insulating layer and a first high-kdielectric layer, and the insulating layer includes a nitride layer andan oxide layer, and the nitride layer is formed between the first high-kdielectric layer and the oxide layer.

In some embodiments, a metal-insulator-metal (MIM) capacitor structureis provided. The MIM capacitor structure includes a CBM layer formed ona substrate, and the CBM layer includes a bottom barrier layer, a mainmetal layer and a top barrier layer. The MIM capacitor structureincludes a first high-k dielectric layer formed on the CBM layer and aninsulating layer formed on the first high-k dielectric layer. Theinsulating layer includes a first nitride layer, a second nitride layer,a first oxide layer and a second oxide layer, and the first oxide layeris formed between the first nitride layer and the second nitride layer.The MIM capacitor structure includes a CTM layer formed on theinsulating layer, and the CBM layer includes a bottom barrier layer, amain metal layer and a top barrier layer.

In some embodiments, a method for forming a metal-insulator-metal (MIM)capacitor structure is provided. The method includes providing asubstrate and forming a capacitor bottom metal (CBM) layer on thesubstrate. The CBM layer includes a bottom barrier layer, a main metallayer and a top barrier layer. The method also includes forming a firsthigh-k dielectric layer on the CBM layer and forming a first nitridelayer on the high-k dielectric layer. The method further includesforming a first oxide layer on the first nitride layer; and forming acapacitor top metal (CTM) layer on the first oxide layer.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A metal-insulator-metal (MIM) capacitorstructure, comprising: a substrate; and a metal-insulator-metal (MIM)capacitor formed on the substrate, wherein the MIM capacitor comprises:a capacitor top metal (CTM) layer; a capacitor bottom metal (CBM) layer;and an insulator formed between the CTM layer and the CBM layer, whereinthe insulator comprises an insulating layer and a first high-kdielectric layer, and wherein the insulating layer comprises a nitridelayer and an oxide layer, and the nitride layer is formed between thefirst high-k dielectric layer and the oxide layer.
 2. Themetal-insulator-metal (MIM) capacitor structure as claimed in claim 1,insulator further comprises a second high-k dielectric layer.
 3. Themetal-insulator-metal (MIM) capacitor structure as claimed in claim 2,wherein the first high-k dielectric layer and the second high-kdielectric layer are formed on opposite sides of the insulating layer.4. The metal-insulator-metal (MIM) capacitor structure as claimed inclaim 1, the first high-k dielectric layer has a relative dielectricconstant in a range from about 4 to about
 400. 5. Themetal-insulator-metal (MIM) capacitor structure as claimed in claim 1,wherein the first high-k dielectric layer comprises titanium oxide(Ti_(x)O_(y), x is a real number and y is a real number), tantalum oxide(Ta_(x)O_(y), x is a real number and y is a real number), titanium oxidenitride (Ti_(x)O_(y)N_(z), x is a real number, y is a real number and zis a real number) or tantalum oxide Nitride (Ta_(x)O_(y)N_(z), x is areal number, y is a real number and z is a real number).
 6. Themetal-insulator-metal (MIM) capacitor structure as claimed in claim 1,wherein the first high-k dielectric layer has a thickness in a rangefrom about 5 angstrom to about 50 angstrom.
 7. The metal-insulator-metal(MIM) capacitor structure as claimed in claim 6, wherein the CBM layercomprises a bottom barrier layer, a main metal layer and a top barrierlayer, and wherein the bottom barrier layer and the top barrier layerare formed on opposite sides of the main metal layer.
 8. Themetal-insulator-metal (MIM) capacitor structure as claimed in claim 7,wherein the first high-k dielectric layer is formed between the topbarrier layer of the CBM layer and the insulating layer.
 9. Themetal-insulator-metal (MIM) capacitor structure as claimed in claim 7,wherein the bottom barrier layer and the top barrier layer independentlycomprise titanium (Ti), titanium nitride (TiN), tantalum (Ta), ortantalum nitride (TaN).
 10. The metal-insulator-metal (MIM) capacitorstructure as claimed in claim 7, wherein the main metal layer comprisescopper (Cu), copper alloy, aluminum (Al), aluminum (Al) alloy, copperaluminum alloy (AlCu), tungsten (W) or tungsten (W) alloy.
 11. Themetal-insulator-metal (MIM) capacitor structure as claimed in claim 1,wherein the insulating layer comprises a silicon nitride layer and asilicon oxide layer.
 12. A metal-insulator-metal (MIM) capacitorstructure, comprising: a CBM layer formed on a substrate, wherein theCBM layer comprises a bottom barrier layer, a main metal layer and a topbarrier layer; a first high-k dielectric layer formed on the CBM layer;an insulating layer formed on the first high-k dielectric layer, whereinthe insulating layer comprises a first nitride layer, a second nitridelayer, a first oxide layer and a second oxide layer, and the first oxidelayer is formed between the first nitride layer and the second nitridelayer; and a CTM layer formed on the insulating layer, wherein the CBMlayer comprises a bottom barrier layer, a main metal layer and a topbarrier layer.
 13. The metal-insulator-metal (MIM) capacitor structureas claimed in claim 12, wherein the first high-k dielectric layercomprises titanium oxide (Ti_(x)O_(y), x is a real number and y is areal number), tantalum oxide (Ta_(x)O_(y), x is a real number and y is areal number), titanium oxide nitride (Ti_(x)O_(y)N_(z), x is a realnumber, y is a real number and z is a real number) or tantalum oxideNitride (Ta_(x)O_(y)N_(z), x is a real number, y is a real number and zis a real number).
 14. The metal-insulator-metal (MIM) capacitorstructure as claimed in claim 12, further comprising: a second high-kdielectric layer formed between the second oxide layer and the CTMlayer.
 15. A method for forming metal-insulator-metal (MIM) capacitorstructure, comprising: providing a substrate; forming a capacitor bottommetal (CBM) layer on the substrate, wherein the CBM layer comprises abottom barrier layer, a main metal layer and a top barrier layer;forming a first high-k dielectric layer on the CBM layer; forming afirst nitride layer on the first high-k dielectric layer; forming afirst oxide layer on the first nitride layer; and forming a capacitortop metal (CTM) layer on the first oxide layer.
 16. The method forforming metal-insulator-metal (MIM) capacitor structure as claimed inclaim 15, further comprising: forming a second high-k dielectric layerbetween the first oxide layer and the CTM layer.
 17. The method forforming metal-insulator-metal (MIM) capacitor structure as claimed inclaim 15, further comprising: forming a second nitride layer on thefirst oxide layer; and forming a second oxide layer on the secondnitride layer.
 18. The method for forming metal-insulator-metal (MIM)capacitor structure as claimed in claim 15, wherein forming the firsthigh-k dielectric layer on the CBM layer comprises: treating a surfaceof the top barrier layer of the CBM layer.
 19. The method for formingmetal-insulator-metal (MIM) capacitor structure as claimed in claim 18,wherein treating the surface of the top barrier layer of the CBM layeris performed by a plasma ionization method, microwave surface downstreamionization method, or furnace/rapid thermal annealing (RTA) method. 20.The method for forming metal-insulator-metal (MIM) capacitor structureas claimed in claim 15, forming the first oxide layer on the firstnitride layer comprises: performing a plasma ionization method on thefirst nitride layer, such that the first oxide layer is formed on thefirst nitride layer.